A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology

Abstract

This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of the conversion rate. A modified StrongARM latch is adopted to further reduce the comparator noise. A calibration procedure runs in the background to address the nonuniform comparator offsets and the interstage gain error. Fabricated in a 28-nm FDSOI process, the prototype ADC achieves an SNDR of 46.65 dB at Nyquist with a power consumption of 2.1 mW, leading into a Walden FOM of 12.01 fJ/conv.-step.