Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS

Abstract

SRAMs consume a large share of power in an advanced SoC. Hierarchical bitlines are used to reduce power consumption. In this work, we compare a Charge Scavenging Gate Coupled (CSGC) Hierarchical Bitline Architecture with the Conventional Memory and Conventional Hierarchical Architecture. While Conventional Hierarchical architecture is more efficient for smaller memory capacity, we show that for large instances operating at low speeds, CSGC scheme can save up to 32% power over Conventional Memory architecture in 65nm LSTP CMOS technology. Also, it saves 15% more power than the Conventional Hierarchical scheme at an additional area overhead of 5%.