Reliability-aware design of metal/high-k gate stack for high-performance SiC power MOSFET

T. Hosoi, Shuji Azumo, Y. Kashiwagi, S. Hosaka, Kenji Yamamoto, M. Aketa, H. Asahara, Takashi Nakamura, T. Kimoto, T. Shimura, Heiji Watanabe
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引用次数: 11

Abstract

Advanced metal/high-k gate stack technology for SiC-based power MOSFET was demonstrated. We found that the Hf incorporation into aluminum oxynitride (HfAlON gate insulator) combined with TIN electrode effectively improves the stability of threshold voltage under both negative and positive bias temperature stresses. Since the relative permittivity of HfAlON increases with increasing Hf content, peak transconductance enhancement up to 3.4 times with acceptable reliability margin was achieved in the state-of-the-art trench MOSFET by implementing TiN/HfA10N(Hf50%) gate stack.
高性能SiC功率MOSFET金属/高k栅极堆的可靠性感知设计
介绍了用于硅基功率MOSFET的先进金属/高k栅极堆叠技术。我们发现,将Hf掺入氮化铝(HfAlON栅绝缘子)并结合TIN电极,可以有效地提高阈值电压在负偏置和正偏置温度应力下的稳定性。由于HfAlON的相对介电常数随着Hf含量的增加而增加,通过实施TiN/HfA10N(Hf50%)栅极堆栈,在最先进的沟槽MOSFET中实现了3.4倍的峰值跨导增强,并具有可接受的可靠性边际。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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