Power consumption analysis in static CMOS gates

Abstract

This paper addresses the power consumption in CMOS logic gates through a study that considers the transistor network arrangement and the advance of the technology node. The relationship between charge/discharge and short-circuit dynamic power components are investigated through electrical simulations (SPICE). The static power dissipation is also analyzed. Experimental results demonstrate that dynamic power still remains the main source of consumption in standard cell designs, although the short-circuit component seems to decrease at the advancing of CMOS fabrication processes. The static power, on the other hand, keeps growing at each new technology node, becoming even more a critical challenge in VLSI design.