A 6-bit bias-less pipelined ADC with open-loop amplifiers

Abstract

This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth preventing the requirement of bias current sources in linear amplification. This bias-less ADC adopts 1.2 V for core circuits and 1.8 V for clocking with power dissipation of 80 mW. Simulation result indicates that the SNDR achieves 35.84 dB and the maximum INL and DNL are 0.4 LSB and 0.5 LSB, respectively.