A monolithic 2.8 V, 3.2 W silicon bipolar power amplifier with 54% PAE at 900 MHz

2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096) Pub Date : 2000-06-10 DOI:10.1109/RFIC.2000.854429

A. Heinz, W. Simburger, H. Wohlmuth, P. Weger, W. Wilhelm, R. Gabl, K. Aufinger

引用次数: 1

Abstract

This work presents a balanced two-stage monolithic power amplifier in Si bipolar technology for 0.8-1 GHz. On-chip transformers are used as input-baluns as well as for interstage matching. A closed-loop bias circuit is introduced to diminish break-down effects and increase the maximum usable supply voltage. The chip is operating from 2.8 V to 4.5 V. At 2.8 V the output power is 3.2 W with a power-added efficiency of 54%. The maximum output power of 7.7 W with an efficiency of 57% is achieved at 4.5 V supply voltage. The small-signal gain is 38 dB.

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单片式 2.8 V、3.2 W 硅双极功率放大器，900 MHz 时 PAE 为 54

这项研究采用硅双极技术，提出了一种 0.8-1 千兆赫的平衡两级单片功率放大器。片上变压器用作输入平衡器和级间匹配。芯片采用了闭环偏置电路，以减少击穿效应并提高最大可用电源电压。芯片的工作电压为 2.8 V 至 4.5 V。在 2.8 V 时，输出功率为 3.2 W，功率附加效率为 54%。在 4.5 V 电源电压下，最大输出功率为 7.7 W，效率为 57%。小信号增益为 38 dB。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)

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