LIPFD-NPU: Low-overhead Instruction-driven Permanent Fault Detection for Neural Processing Unit

Abstract

Neural Processing Unit (NPU) has become the state-of-the-art solution for accelerating artificial neural networks and is increasingly integrated on the System-on-Chip (SoC) of edge devices such as smartphones and cameras. However, adopting NPU in mission-critical systems, such as aerospace aircraft and autonomous driving demands high reliability, which is currently less explored on industrial NPUs. In this work, we target one of the critical reliability issues - permanent fault - for modern NPUs and provide an instruction-driven fault detection method named LIPFD-NPU. The approach executes dedicated network instructions in a self-testing fashion and generates fine-grained information on the potential fault's location, type and level of impact. An FPGA-based fault emulation framework is used to verify LIPFD-NPU. The results indicate that LIPFD-NPU effectively detects faults with tiny overheads of 0.2% in silicon area and 0.5% in power consumption.