Design Guidelines and Limitations of Multilayer Two-dimensional Vertical Tunneling FETs for UltraLow Power Logic Applications

Abstract

New designs for vertical 2D-materials-based TFETs are proposed in this paper adopting asymmetric layer numbers for the top and bottom layer with undoped source/drain using Black Phosphorus as an example. The results show that abrupt turn-on and Ion/Ioff > 105 can be sustained when the channel length is down to sub-5 nm. The results are benchmarked against other TFETs based on promising 2D materials homo-/hetero-structures, meanwhile, the limitations, as well as guidelines, are presented.