Integrated circuit EDA design of 10-bit SAR ADC with low power

Abstract

A 10-bit 1Ms/ps SAR ADC with low power is designed by integrated circuit EDA software, which is realized in a 0.18um CMOS process. The design combines a capacitor DAC, a CMOS dynamic comparator, a SAR digital logic control cell, and a two phase non-overlap clk cell. Through the EDA simulation results, the SAR ADC designed in this paper is suited for low power operation with 30.3 uW from a 1.8V voltage supply, and the input range is rail to rail‥1