Specifications and FPGA implementation of a systolic Hopfield-type associative memory

Abstract

Neural networks are non-linear static or dynamical systems that learn to solve problems from examples. Most of the learning algorithms require a lot of computing power and, therefore, could benefit from fast dedicated hardware. One of the most common architectures used for this special-purpose hardware is the systolic array. The design and implementation of different neural network architectures in systolic arrays can be complex, however. The paper shows the manner in which the Hopfield neural network can be mapped into a 2-D systolic array and presents an FPGA implementation of the proposed 2-D systolic array.