FPGA Implementation for Direct Kinematics of a Spherical Robot Manipulator

Abstract

The sequential behavior of general purpose processors presents limitations in applications that require high processing speeds. One of the advantages of FPGAs implementations is the parallel process capability, allowing acceleration of complex algorithms. Nowadays it is common to find FPGA implementations in applications requiring high speed processing. In this paper a hardware architecture for computing direct kinematics of robot manipulators using floating-point arithmetic is presented for 32, 43 and 64 bit-width representations. Otherwise, the processing time of the hardware architecture is compared with the same formulation implemented in software, using the PowerPC (FPGA embedded processor). The proposed architecture was validated using Matlab results as a statistical estimator in order to compute the Mean Square Error (MSE). Synthesis and simulation results demonstrate the accuracy and high performance of the implemented hardware architecture.