Enhance hardware security using FIFO in pipelines

Abstract

Cryptographic functions are foundation of many information security applications. Embedded cryptographic hardware is vulnerable to side channel attacks such as power analysis- and fault- attacks. In this paper, we propose a design architecture which enhances the hardware security against such attacks. The key idea is to insert FIFOs in between two successive pipeline stages and randomly vary the duration when the data stay at FIFOs in every pipeline loop. This can make the time instant of executing certain operation unpredictable. The more timing variation appears, the less probability the attack succeeds. The proposed approach provides more possible configurations than previous approaches as well as it can be realized in both ASIC and FPGA implementations. We implemented the required controller and data path. Furthermore, the AES (Advanced Encryption Standard) algorithm was realized with the proposed pipeline of four stages.