A simulation efficiency improvement method for simulation-based analog cell synthesis

Abstract

This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency. For the hierarchical synthesis of analog cell we developed sub-circuit optimizers such as the current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA (operational transconductance amplifier), 2-stage op-amp and comparator. To reduce the time spent on the simulation-based synthesis, we propose a two-stage searching scheme and simulation data reuse scheme. With these schemes the synthesis time spent on the OTA was reduced from 301.05 s to 56.52 s, i.e. by 81.1%. Since our synthesis system does not need other additional physical parameters except SPICE parameters, and is independent of the process and its model level, the time spent to port to other process is minimized. We synthesized an OTA and 2-stage op-amp respectively with our approach to show its usefulness.