CNPC deinterleaver implementation to increase hardware logic utilization on FPGA

Abstract

The UAV has been used in various fields, and is gradually expanding its application fields. To safely operate the UAV, the stable communication system for command is standardized in RTCA and the standardization is described in MOPS. In MOPS, transmitter uses interleaver module as the one of the components. This interleaver module is used to avoid the burst errors in transmission. Use of interleaver module in transmitter, requires deinterleaver to reorder the shuffled transmitter signal. To implement this module in the real world, the FPGA is used as the hardware. The implementation on FPGA requires for developers to understand the parallel processing. Moreover, deinterleaver accepts the symbol with multi bit as the input. This means that a lot of RAM has to be used for the deinterleaver matrix. To implement a module requiring a lot of RAMs, FPGA uses BRAMs despite the situation where LUT RAMs remain. To develop deinterleaver module utilizing LUT RAMs as possible in the FPGA, this paper introduces the timing diagram for the scheme.