Circuit Partitioning Problem Clustering Method Based on Adjacency Matrix Unification

Abstract

The present work deals with artificial intelligence research. The problem of engineering software benchmarking study for the purpose of fitting for task type and computational resources is important today. This problem is often solved by the help of intelligence decision support systems (IDSS). Domain ontology is a typical knowledge representation model in such systems. Manual ontology development is a time-consuming and expensive process. Because of a great variety of circuit partitioning problem formulization, clustering is a necessary step of automated circuit partitioning problem ontology development. The problem of automated circuit partitioning problem clustering appears because of integrated data comparison. This data is represented by different dimension structures. The goal of this work is the development of circuit partitioning problem clustering method based on adjacency matrix unification. The hypergraph model of circuit representation was chosen, circuit partitioning problem was formalized. The case of adjacency matrix with different dimension clustering was observed. The novelty of proposed method is the inclusion of matrix with different dimension unification procedure in the generic clustering method.