Reduced Triple Modular redundancy for built-in self-repair in VLIW-processors

Abstract

In this paper we propose a new idea for built-in-self-repair of application specific VLIW processors, which relies on a special kind of triple modular redundancy, which we call Reduced Triple Modular Redundancy (RTMR). The key idea is to employ the redundancy of operators in the data path of a VLIW processor. I.e., every operation is executed twice by two different operators during normal program execution. Only in case a mismatch between both computed results occurs, the operation is executed by a third operator. Therefore, during most of the execution time, the third operator can be used for executing regular operations of the program. We propose modifications of the VLIW architecture in order to detect a mismatch in computed results. Necessary program transformations are introduced, in order to obtain an internal representation for fault tolerant programs that can be scheduled to the proposed VLIW architecture. Furthermore, we propose the program execution model that is used in case a permanent fault in the data path has been detected and give some preliminary results.