On-demand reconfiguration for coprocessors in mixed criticality multicore systems

Viet Vu Duy, O. Sander, T. Sandmann, Jan Heidelberger, S. Bähr, J. Becker
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引用次数: 4

Abstract

Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In a previous work, we proposed a concept that leverages the advantages of FPGA's partial reconfiguration in heterogeneous mixed criticality multicore systems. The basic idea how to handle the partial reconfiguration transparently for noncritical tasks, while providing full control and a predictable behavior for safety relevant tasks was described. In this paper, we focus on the on-demand partial reconfiguration of coprocessors and its implementation details. Our prototype is implemented on an Intel multicore system and a Xilinx Virtex-7 FPGA connected via PCI Express, taking advantage of the Single-Root I/O Virtualization capabilities in modern PCI Express implementations. Experimental results show that compared to the reference software implementation, our concept achieves significantly shorter reconfiguration time with lower variance under various system load situations.
混合临界多核系统中协处理器的按需重构
特别是在复杂的系统的场景中,多个高性能或实时处理功能需要共存和交互,可重构设备与虚拟化技术一起显示出相当大的希望,以提高效率,简化集成和维护单个功能的功能和非功能属性。在之前的工作中,我们提出了一个概念,利用FPGA在异构混合临界多核系统中的部分重构优势。描述了如何透明地处理非关键任务的部分重构,同时为安全相关任务提供完全控制和可预测行为的基本思想。本文重点讨论了协处理器的按需部分重构及其实现细节。我们的原型是在Intel多核系统和Xilinx Virtex-7 FPGA上实现的,通过PCI Express连接,利用了现代PCI Express实现中的单根I/O虚拟化功能。实验结果表明,与参考软件实现相比,我们的概念在各种系统负载情况下实现了更短的重构时间和更小的方差。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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