Hot electron induced channel length shortening model and its impact on HEIP in PMOS

Abstract

A new analytical model based on a pseudo two dimensional model is presented for the hot electron induced channel length shortening (/spl Delta/L/sub H/) of PMOSFET. It has been founded that /spl Delta/L/sub H/ is a logarithmic function of both the stress time and the degradation of punchthrough voltage, and is also a linear function of the degradation of the drain current. /spl Delta/L/sub H/ can be predicted from the measurement of the gate current (/spl Delta/L/sub H//spl prop/I/sub g//sup n/) and can thus be used for the current calculation of a degraded PMOSFET.