A Low Power 0.6V Filter-less AD-PLL with a Fast Locking Algorithm in the Subthreshold Region

Abstract

A fast locking algorithm for use in a Filter-less All-digital PLL (AD-PLL) is presented in this paper. This algorithm makes it possible to replace the low pass filters and charge pumps used in conventional PLLs with a Time-to-digital converter with small area, while reducing lock time. The full system was implemented using 0.18µm CMOS technology and simulated with HSPICE using the extracted layout RC parasitics. The circuit uses a 0.6V supply for operation in the subthreshold region. Results show that the Filter-less AD-PLL is able to lock within 23 cycles of a 1MHz reference signal while consuming less than 26µW for all configurations of a Programmable Frequency Divider in the feedback path.