Increase of convertor efficiency and suppression of parasitic bipolar by means of process optimization

Abstract

Power Management Integrated Circuits (PMIC) chips contain large power switches - usually LDMOS transistors, along with low current control circuitry. During transistor switching, charge carriers are injected into the substrate and affect the surrounding devices. In junction isolated technologies, hole injection is effectively suppressed using highly doped n-type layers, while electron injection requires separating the highly doped layer from the drain of the device. However, this architecture forms a parasitic NPN transistor, which conducts the injected electrons to the isolation layer causing efficiency losses. We present here a method to improve the efficiency of the switch, by altering the semiconductor doping and thus tuning the gain of the parasitic bipolar. A clear tradeoff between gain and breakdown of the parasitic NPN is discussed.