A 0.8V/0.6V 2.2μW Time-Domain Analog Front-End with $540\text{mV}_{\text{pp}}$ Input Range, 81.6dB SNDR and $80\mathrm{M}\Omega$ Input Impedance

Abstract

The next generation autonomous sensor nodes are being developed towards ultra-low-power with on-node signal processing capability. The former facilitates battery-less and miniaturized sensors relying on harvested energy, while the latter enables intelligent System-on-Chip (SoC) to sense and process multimodal parameters locally on the sensor nodes. As for analog front-end (AFE), a straightforward solution for low power and digital compatibility is to reduce its supply voltage to the sub-volt range. However, supply scaling is less friendly to conventional AFEs, which often require large dynamic range (DR) and high linearity, Furthermore, practical considerations of low noise, high input-impedance $(\mathrm{Z}_{\text{in}})$ and sensor-dependent bandwidth (BW) further exacerbate the challenges to comply with versatile sensors. To realize the low-voltage AFE, time-domain (TD) direct digitization architectures [1]–[5] were proposed (Fig. 1). The $\mathrm{G}_{\mathrm{m}}-\mathrm{C}$ based delta-sigma modulator $(\Delta\Sigma \mathrm{M})$ with a built-in TD loop filter benefits from high input impedance and higher order noise shaping [1], but the $\mathrm{G}_{\mathrm{m}}$ exhibits nonlinearity for a large input signal. Alternatively, the VCO-based AFEs provide better supply voltage scalability and inherent ${1}^{\text{st}}$-order noise shaping. The open-loop VCO-based AFE [2] benefits from a small chip area, but suffering from the tradeoff between linearity and input range. While the closed-loop VCO-based AFE solves this issue [3]–[5], this topology often needs a highly linear feedback DAC that notably reduces the input impedance of the AFE, unless impedance boosting buffers are used [6]. Besides, the closed-loop VCO based AFEs needs to be clocked continuously, resulting in power overhead.