Comparison of performance of high speed VLSI adders

Abstract

In modern VLSI design, the occurrence of delays is predictable. Many digital systems that process data may have delays. Design requires thorough understanding of algorithms, recurrence structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this research work, 16-bit and 64 bit adder is designed and comparison is made between all types of adders in terms of delay. Xilinx ISE is used for simulation and synthesis Delay of 13.88 ns for a 16 bit Ling adder and 64 bit Sparse 2 adder has a delay of 35.026 ns. Area is also measured and comparison is made.