An 11-bit 250MS/s subrange-SAR ADC in 40nm CMOS

Abstract

This paper presents an 11-bit 250MS/s subrange SAR ADC. The subrange SAR ADC in this paper consists of coarse conversions of 4-bit flash ADC and fine conversions of 8-bit SAR ADC, which fully combines high speed of flash ADC and low power consumption of SAR ADC. The design is fabricated in a 40nm low-leakage process, and the core area is 0.018mm2. The post layout simulation achieves an ENOB of 9.99 bits at Nyquist input and consumes 1.5mW from 1.1V supply, leading to a FOM of 5.86fJ/conv-step.