A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators

B. Young, K. Reddy, Sachin Rao, A. Elshazly, Tejasvi Anand, P. Hanumolu
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引用次数: 27

Abstract

A wide bandwidth, high sample rate 3rd order continuous-time ΔΣ modulator using VCO-based integrators is presented. Non-idealities caused by VCOs at the modulator frontend are addressed using both circuit- and architecture-level techniques. Fabricated in 65 nm CMOS, the prototype modulator operates at 1.28 GS/s and achieves a dynamic range of 75 dB, SNR of 71 dB in 50 MHz bandwidth, while consuming 38 mW of total power.
采用基于vco的积分器的75dB DR 50MHz BW三阶CT-ΔΣ调制器
提出了一种基于vco积分器的宽带宽、高采样率三阶连续时间ΔΣ调制器。由调制器前端的vco引起的非理想性使用电路级和体系结构级技术来解决。该原型调制器采用65 nm CMOS工艺,工作速度为1.28 GS/s,在50 MHz带宽下动态范围为75 dB,信噪比为71 dB,总功耗为38 mW。
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