LEAP: A Deep Learning based Aging-Aware Architecture Exploration Framework for FPGAs

B. Ghavami, Seyed Milad Ebrahimi, Zhenman Fang, Lesley Shannon
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Abstract

Transistor aging raises a vital lifetime reliability challenge for FPGA devices in advanced technology nodes. In this paper, we design a tool called LEAP to enable the aging-aware FPGA architecture exploration. The core idea of LEAP is to efficiently model the aging-induced delay degradation at the coarse-grained FPGA basic block level using deep neural networks (DNNs), while achieving almost the same accuracy as the transistor-level simulation. For each type of the FPGA basic block such as LUT and DSP, we first characterize its accurate delay degradation via transistor-level SPICE simulation under a versatile set of aging factors from the FPGA fabric and in-field operation. Then we train one DNN model for each block type to learn the relation between its delay degradation and aging factors. Moreover, we integrate our DNN models into the widely used Verilog-to-Routing (VTR 8) toolflow and generate the aging-aware FPGA architecture file. Experimental results demonstrate that our proposed flow can predict the delay degradation of FPGA blocks more than 104x to 107x faster than transistor-level SPICE simulation, with the maximum prediction error of less than 0.7%. Therefore, FPGA architects can leverage LEAP to explore better aging-aware FPGA architectures.
基于深度学习的fpga老化感知架构探索框架
晶体管老化对先进技术节点中FPGA器件的寿命可靠性提出了重要挑战。在本文中,我们设计了一个名为LEAP的工具来实现FPGA的老化感知架构探索。LEAP的核心思想是利用深度神经网络(dnn)在粗粒度FPGA基本块级有效地模拟老化引起的延迟退化,同时达到与晶体管级模拟几乎相同的精度。对于每种类型的FPGA基本块(如LUT和DSP),我们首先通过晶体管级SPICE仿真在FPGA结构和现场操作的多种老化因素下表征其准确的延迟退化。然后,我们为每个块类型训练一个DNN模型,以学习其延迟退化与老化因素之间的关系。此外,我们将我们的DNN模型集成到广泛使用的Verilog-to-Routing (VTR 8)工具流中,并生成老化感知的FPGA架构文件。实验结果表明,该流程预测FPGA块延迟退化的速度比晶体管级SPICE仿真快104 ~ 107倍,最大预测误差小于0.7%。因此,FPGA架构师可以利用LEAP来探索更好的老化感知FPGA架构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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