Hardware Implementation of 5G NR Deinterleaver and De-rate Matcher

Abstract

5G new radio (NR) represents the newest standard for mobile communications. It introduced LDPC channel coding which enables increased spectral efficiency in comparison to turbo codes used in LTE. It also specifies throughputs in the order of tens of Gb/s at lower latencies, putting a challenging constraint on all components in the data chain. In this paper, a parallel high throughput architecture of a joint deinterleaver and derate matcher for 5G NR is proposed. Efficient and scalable nature of the architecture allows easy tuning of throughput versus utilization over a large range of values. Proposed scheme for LLR value storage enables efficient memory utilization with full read and write throughput. The proposed architecture was implemented on a Zynq Ultrascale+ RFSoC FPGA from Xilinx in order to verify the functionality. Implementation achieves clock frequency close to the highest possible on the given architecture. To the best of our knowledge, this is currently the highest throughput implementation available.