Embedded Concurrent Computing Architecture using FPGA

Abstract

Simultaneous multithreading by use of embedded parallel systolic filters is a novel technological approach to achieve multiprocessing. It is important for the designers to ensure that FPGA chips that are fully operational. There is great emphasis on the design area, performance, challenges and opportunities posed by multi-tasking as a result of the huge number of inputs and outputs required by the design. The Embedded Concurrent Computing Architecture proposed is implemented on a FPGA chip. There are expected speedups in the implementation based on the results shown in this proposal. Synthesis has been used in gathering of the results with implementation being achieved by use of low complexities in the FPGA usage and frequency. The efficiency of the new model is over 75% with the performance of the design is secured for a tolerance of 2 m for 25 m range. The Particle filter tolerance is less than 1m with an operating frequency of 212 MHz or thereabouts.