Design and Analysis of Double-Tail Dynamic Comparator for Flash ADCs

Abstract

This paper present an analysis of delay and power of the dynamic comparator. As the need for high speed, area efficient and low power analog to digital converters. We are force to go through the dynamic regenerative comparators to maximize speed and power efficiency. A new double tail dynamic comparator is proposed from conventional double-tail comparator for low power and fast operation for low voltage. The new double-tail dynamic comparator reduced delay significantly. At the supply voltage of 1.8V and the sampling frequency of 1.25GHz, the delay and average power of the comparator is 116.2ps and 347.27μW. The proposed dynamic comparator is suitable for flash ADCs. The circuits are simulated with 180nm CMOS- technology in cadence virtuoso. Post-layout analysis of the circuit is done with DRC and LVS check.