Sparse-HeteroCL: From Sparse Tensor Algebra to Highly Customized Accelerators on FPGAs

Abstract

Hardware-oriented domain-specific languages and hardware autogeneration pipelines for computationally intensive applications have received widespread attention because they can reduce the complexity of custom accelerator design and enable efficient FPGA accelerator generation. However, the existing hardware autogeneration tools are intended only for general computing and lack support for sparse tensor computation. To solve this problem, we present an end-to-end compilation tool called Sparse-HeteroCL, which inherits the idea of decoupling algorithm specification and customization from HeteroCL and expands it in three aspects: data structure, program description and computation schedule. In a preliminary performance evaluation, the workload incurred when using this compilation tool to write sparse tensor accelerators was compared with the corresponding workloads based on HeteroCL and HDL. The results show that compared with these existing languages, the programming efficiency is increased by average factors of 5.94 and 386.7, respectively, using our compilation tool.