Formal Verification of Device State Chart Models

Abstract

Design and development of increasingly complex intelligent environments require rich design flows that include strong validation and verification methodologies. Formal verification techniques are often advocated, and they require formally described models of the smart home devices, their interconnections, and their controlling algorithms. Complete verification can only be achieved if all used models are verified, including individual device models. This paper proposes an approach to formally verify the correctness of device models described as UML State Charts, by checking their consistency with respect to the properties, declared in an Ontology, for the categories to which each device belongs. The paper describes the verification methodology and presents some first verification results.