Ultra-low resistance W/Si/sub 1-x/Ge/sub x//Si source-drain contacts

Y. Chieh, J.P. Krusius, D. Green, M. Ozturk
{"title":"Ultra-low resistance W/Si/sub 1-x/Ge/sub x//Si source-drain contacts","authors":"Y. Chieh, J.P. Krusius, D. Green, M. Ozturk","doi":"10.1109/DRC.1995.496233","DOIUrl":null,"url":null,"abstract":"Fabrication of CMOS devices with feature sizes on the order of 100 nm will require junction depths of less than 70 nm in order to control short-channel effects. Fully-scaled 100x100 nm/sup 2/ source-drain regions in such devices will require contact resistivities of less than 10/sup -7/ ohm-cm/sup 2/ in order not to reach limits on currents. A W contact technology was been pursued in this work. W can be be deposited selectively with little substrate consumption and it has been shown to have a low contact resistivity on n+ Si. Si/sub x/Ge/sub 1-x/ has the further potential advantage of lowered tunnel barrier heights to p+ Si because of the reduced bandgap. Therefore there is a possibility for improving contact resistivities to p+ Si as well. Finally, W is an excellent barrier metal with good thermal stability both for Si and Si/sub x/Ge/sub 1-x/.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 53rd Annual Device Research Conference Digest","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.1995.496233","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Fabrication of CMOS devices with feature sizes on the order of 100 nm will require junction depths of less than 70 nm in order to control short-channel effects. Fully-scaled 100x100 nm/sup 2/ source-drain regions in such devices will require contact resistivities of less than 10/sup -7/ ohm-cm/sup 2/ in order not to reach limits on currents. A W contact technology was been pursued in this work. W can be be deposited selectively with little substrate consumption and it has been shown to have a low contact resistivity on n+ Si. Si/sub x/Ge/sub 1-x/ has the further potential advantage of lowered tunnel barrier heights to p+ Si because of the reduced bandgap. Therefore there is a possibility for improving contact resistivities to p+ Si as well. Finally, W is an excellent barrier metal with good thermal stability both for Si and Si/sub x/Ge/sub 1-x/.
超低阻W/Si/sub - 1-x/Ge/sub -x/ /Si源漏触点
为了控制短通道效应,制造特征尺寸为100 nm的CMOS器件需要小于70 nm的结深。这种器件的全尺寸100x100nm /sup 2/源漏区域将要求接触电阻率小于10/sup -7/欧姆-cm/sup 2/,以避免达到电流限制。研究了一种W接触技术。W可以选择性地沉积,衬底消耗很少,并且在n+ Si上具有低接触电阻率。Si/sub x/Ge/sub 1-x/由于减小了带隙,具有进一步降低隧道势垒高度到p+ Si的潜在优势。因此,也有可能提高p+ Si的接触电阻率。最后,W对于Si和Si/sub -x/ Ge/sub - 1-x/都具有良好的热稳定性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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