A field-programmable digital filter chip using multiple-valued current-mode logic

Abstract

This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The prototype FPDF fabrication with 0.6 /spl mu/m CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 74%, respectively, compared with the standard binary logic implementation.