Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

Abstract

A memory array configuration and a decoder circuits for the DINOR flash memory have been described. The hierarchical row decoder and the compact source line driver realize 1K byte sector erasure without increasing the decoder area. The decoder pitch has been relaxed to one driver per two word lines. Narrow threshold voltage distribution has been realized by the bit-by-bit programming control and the low threshold voltage detection circuit, which achieves high speed random access time at low Vcc. A 4 Mb test device was fabricated in a 0.5 /spl mu/m CMOS triple well process and a typical access time of 90 ns was obtained at Vcc of 3 V.