The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates

Abstract

The Enhanced Scouting Logic (ESL) is a memristive logic gate family with low sensitivity to resistance variation and high device endurance. This work studies the design methods of logic circuits based on the Voltage-Input Enhanced Scouting Logic (VIESL) gates. Both the single-array and dual-array synthesis methods are proposed. The read/write separation technique of VIESL gates facilitates the pipelined logic operations. The synthesis results on the benchmarks show that the circuit generated by the proposed single-array synthesis method has the best performance compared with that of its counterparts, and the dual-array synthesis method reduces the cell counts effectively.