Evaluation and Performance Comparison of TriBA with existing On-Chip Interconnection Networks

Abstract

This paper evaluates the performance of triplet based architecture, TriBA - a new idea in multiprocessor architectures. TriBA is compared with two types of static interconnection networks for VLSI implementation. The interconnection networks used for comparison are well-known in literature as two-dimensional mesh and binary tree. The evaluation criteria has been selected from three orthogonal entities - physical (chip area and dissipation), computational speed (message delay) and cost (chip yield, layout cost). TriBA is a new solution for computer architecture, which is believed to be suitable for sophisticated embedded applications with multiple concurrent processing centers. TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors. TriBA is an object-oriented chip multi-processor structure that supports truly parallel execution of objects from hardware. Cores on the same chip are connected via triplet-based hierarchical interconnection network (THIN), which has simple topology and computing locality characteristic. The root of "triplet based architecture" is based on the concept that "complex problems can be decomposed to three relatively independent sub-problems, which are data processing, data management and data communication" TriBA manifests great similarity to the hierarchal structure of object systems, so that the software and computer system achieve a certain degree of structural unity.