Area-high speed design trade-offs for advanced encryption standard cipher engine

Abstract

For secure data transmission cryptographic algorithms are used for many applications. This paper introduces optimized hardware implementation of area and speed improvement for the block cipher Advanced Encryption Standard (AES-128) using Field Programmable Graphic Array (FPGA). As AES has four transformations among them sub-byte and mix-column transformation are key challenges to implement in terms of area and speed. The proposed implementation proposes new method cyclic shift method for implementation of mix-column transformation which uses logical shift and XOR operation. This hardware implementation achieves throughput 1164.788 Mbps at the maximum clock frequency of 100.099 MHz is, in feedback encryption modes and uses less number of slices 2081.