{"title":"A Novel Fast-Switching 5-GHz Phase-Interpolator with Superior Linearity in 65-nm CMOS Technology","authors":"Muhamed F. Allam, H. Omran, S. Ibrahim","doi":"10.1109/NRSC52299.2021.9509782","DOIUrl":null,"url":null,"abstract":"This paper presents a fast-switching phase-interpolator (PI) operating at 5-GHz with superior linearity. The PI is designed for high bandwidth clock and data recovery (CDR) to enable high jitter-tolerance (JTOL) in serial-link applications. It is based on a current-switching topology to enable a high phase-update rate. It also employs an adaptive regenerative amplifier (ARA) to prevent amplitude-dependent delays. This PI consists of cascaded trigonometric phase-interpolator (TPI) and linear phase-interpolator (LPI) stages together with cross-coupled devices load to immensely enhance its linearity, enabling an 8-bit resolution with an integral nonlinearity (INL) of 0.5 LSB and differential nonlinearity (DNL) of 0.15 LSB. The PI is implemented in 65-nm CMOS technology, operating under a 1.2 V supply with a current consumption of 26mA.","PeriodicalId":231431,"journal":{"name":"2021 38th National Radio Science Conference (NRSC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 38th National Radio Science Conference (NRSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NRSC52299.2021.9509782","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a fast-switching phase-interpolator (PI) operating at 5-GHz with superior linearity. The PI is designed for high bandwidth clock and data recovery (CDR) to enable high jitter-tolerance (JTOL) in serial-link applications. It is based on a current-switching topology to enable a high phase-update rate. It also employs an adaptive regenerative amplifier (ARA) to prevent amplitude-dependent delays. This PI consists of cascaded trigonometric phase-interpolator (TPI) and linear phase-interpolator (LPI) stages together with cross-coupled devices load to immensely enhance its linearity, enabling an 8-bit resolution with an integral nonlinearity (INL) of 0.5 LSB and differential nonlinearity (DNL) of 0.15 LSB. The PI is implemented in 65-nm CMOS technology, operating under a 1.2 V supply with a current consumption of 26mA.