High-speed power MOSFET with low reverse transfer capacitance using a trench/planar gate architecture

Abstract

A trench/planar MOSFET (TP-MOS) is proposed in this work as a high speed switching device. The device is comprehensively studied with numerical simulations, and comparisons are made with the conventional MOSFET (C-MOS) and the split-gate MOSFET (SG-MOS). Compared to the C-MOS, the removal of the MOS-structure above the JFET region results in a dramatic reduction of the reverse transfer capacitance (Crss) in the SG-MOS and TP-MOS. The top p-base in the TP-MOS expedites the depletion in the JFET region, which helps further reduce the Crss and alleviates the electric field crowding. The additional trench channels in the TP-MOS lowers the total channel resistance, which compensates the increase of JFET resistance caused by the absence of the electron accumulation layer under the MOS-structure. Therefore, the TP-MOS achieves the best RON-Crss trade-off.