Pitfalls in ADC Characterization: Getting those extra dBs

Abstract

With complex applications and system requirements, the level of integration in modern day SoCs have increased many folds. Analog to digital Converters (ADCs) are important part of many networking and communication chips. Higher data rate requirements need ADC that can operate at high speed without much compromise in performance. As the speed, complexity and number of Analog to Digital Converters increases in a SoC, it makes its characterization and validation a challenging task. Though the tests that need to be performed are well defined in theory, performing those tests accurately to evaluate the system’s true performance is vital. The results obtained may not be as accurate as they seem, resulting in underestimating the product specifications. This paper focuses on pitfalls of dynamic measurements and propose methods to overcome them for true and accurate measurements of the Device Under Test (DUT). We also propose efficient and robust algorithms which can ease the process of calibration for more refined characterization.