Application-specific network-on-chip design space exploration framework for neuromorphic processor

Abstract

Neuromorphic processors can support the design of various Spiking Neural Networks (SNN) to deal with different tasks, such as recognition and tracking. Neuromorphic processors use Network-on-Chip (NoC) to support communication between neurons in SNN. The different SNN has different communication traffic patterns. It will pose the different challenges of the NoC designing. A reasonable NoC architecture can improve the overall performance such as lower latency of the processor. Hence, it is critical to implement the exploration of NoC architecture design for neuromorphic processors. This paper proposes a rapid NoC design space exploration (DSE) framework. As to our knowledge, it is the first work for the NoC DSE for the neuromorphic processor. The framework takes the spikes of the SNN application as input. It can support multiple optimization objectives for NoC design. Meanwhile, an optimized simulated annealing algorithm has been used to perform the DSE for the NoC design space. Then it outputs the final NoC design configuration. We apply this framework to 7 SNN applications to perform the NoC DSE. Compared with baseline NoC configuration, the NoC DSE framework can improve performance (Average Transport latency) by 54% to 93%. Compared with the Simulated Annealing (SA) algorithm, the Better-History SA (BHSA) algorithm speeds up the searching process by 1.5 to 8 times.