An efficient antilogarithmic converter by using 11-regions error correction scheme

Abstract

An efficient hardware implementation of logarithmic operations is a good choice in place of binary arithmetic operations. In this paper, we suggest an efficient antilogarithmic converter by using 11-region bit-level manipulation scheme by using the error correction scheme. The proposed hardware minimization technique provides a hardware (area, delay & power) efficient implementation at the same error cost. Existing and proposed antilogarithmic converters design is implemented on Xilinx ISE 12.1. Both converters design are evaluated on the Synopsys design compiler by using SAED 65 nm CMOS library and compared the results concerning of Data Arrival Time (DAT), Area, Power, Area Delay Product (ADP), and Energy. The proposed converter involves 52.33 % less ADP and 41.05 % Energy in comparisons of the existing two-bit regions antilogarithmic converter.