Automatic building of graphs for rectangular dualisation (IC floorplanning)

Abstract

Rectangular dualisation is used to generate rectangular topologies in top-down floorplanning of integrated circuits. The author presents an efficient algorithm that transforms an arbitrary graph, representing a custom integrated circuit into one suitable for rectangular dualisation. The algorithm uses efficient techniques in graph processing, such as planar embedding, and introduces a novel procedure to transform a tree of biconnected subgraphs into a block neighborhood graph that is a path.<>