ESD-Immunity Influence of 60-V pLDMOS by Vertical Floating Polysilicons on the Drain-side STI

Abstract

In this paper, the area effect of floating polysilicons above the drain-side STI on ESD robustness of high voltage components is studied by 0.25-μm 60-V p-channel LDMOS devices. In general, near the gate and drain-side STI regions have high lateral electric-field peaks. Therefore, some floating polysilicon islands above this STI region can be used to reduce the electric-field peak (to increase the breakdown voltage), and then to evaluate its ability of ESD improvement. There are five kinds of width modulation by the vertical arrangement. From the experimental data, the breakdown voltage of pLDMOSs will increase slightly after embedding these vertical floating polysilicon, the trigger voltage will gradually increase by 0∼2V with increasing the floating polysilicon width. Meanwhile, comparing with the reference device ($I_t2$= 0.758 A), the highest secondary breakdown-current ($I_t2$) can be upgraded to 1.042 A and increased about 38%.