Sobel edge detection system design and integration on an FPGA based HD video streaming architecture

Abdelkader Ben Amara, E. Pissaloux, Mohamed Atri
{"title":"Sobel edge detection system design and integration on an FPGA based HD video streaming architecture","authors":"Abdelkader Ben Amara, E. Pissaloux, Mohamed Atri","doi":"10.1109/IDT.2016.7843033","DOIUrl":null,"url":null,"abstract":"Complex image processing algorithms (e.g. Sobel edge detection) combined with higher resolution video streaming, are so computationally and put bigger demands on processing power. Unlike the software solutions, parallel solutions satisfy well these algorithms' performance, but using a programmable logic such as FPGA's can provide us more. Driven by the rapid technological advances, today it's possible to combine a high-speed CPU and an FPGA technology on a single system on Chip (SoC), such as the Xilinx Zynq 7000 series. In this paper, we present a HD video streaming architecture and a Sobel edge detection IP core design and implementation using a high-level synthesis workflow. A HD video with a 1080p resolution streamed from a laptop HDMI interface. The processed videos were displayed by the use of a monitor. For implementation, we used a Digilent ZYBO Zynq ZC7010 based platform and our experimental results will be compared with an NVIDIA M840 GPU.","PeriodicalId":131600,"journal":{"name":"2016 11th International Design & Test Symposium (IDT)","volume":"226 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 11th International Design & Test Symposium (IDT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IDT.2016.7843033","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17

Abstract

Complex image processing algorithms (e.g. Sobel edge detection) combined with higher resolution video streaming, are so computationally and put bigger demands on processing power. Unlike the software solutions, parallel solutions satisfy well these algorithms' performance, but using a programmable logic such as FPGA's can provide us more. Driven by the rapid technological advances, today it's possible to combine a high-speed CPU and an FPGA technology on a single system on Chip (SoC), such as the Xilinx Zynq 7000 series. In this paper, we present a HD video streaming architecture and a Sobel edge detection IP core design and implementation using a high-level synthesis workflow. A HD video with a 1080p resolution streamed from a laptop HDMI interface. The processed videos were displayed by the use of a monitor. For implementation, we used a Digilent ZYBO Zynq ZC7010 based platform and our experimental results will be compared with an NVIDIA M840 GPU.
Sobel边缘检测系统的设计与集成基于FPGA的高清视频流架构
复杂的图像处理算法(如Sobel边缘检测)与更高分辨率的视频流相结合,计算量大,对处理能力的要求更高。与软件解决方案不同,并行解决方案很好地满足了这些算法的性能,但使用可编程逻辑(如FPGA)可以提供更多。在快速技术进步的推动下,今天可以将高速CPU和FPGA技术结合在单个片上系统(SoC)上,例如Xilinx Zynq 7000系列。在本文中,我们提出了一个高清视频流架构和一个Sobel边缘检测IP核的设计和实现,使用高级合成工作流。1080p分辨率的高清视频从笔记本电脑的HDMI接口流。经过处理的视频通过显示器显示出来。为了实现,我们使用了Digilent ZYBO Zynq ZC7010平台,我们的实验结果将与NVIDIA M840 GPU进行比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信