Design of a multilevel DRAM with adjustable cell capacity

Y. Xiang, B. Cockburn, D. Elliott
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引用次数: 13

Abstract

A multilevel DRAM (MLDRAM) increases the per-cell storage capacity over conventional DRAM by using more than two cell signal levels. The key challenge when designing an MLDRAM is to ensure reliable operation using the more closely spaced signal levels despite the presence of on-chip noise and the inevitable small variations in circuit parameters that occur in integrated circuit (IC) production. This paper describes a test chip that implements an inherently balanced and robust MLDRAM scheme proposed by Birk et al. (see 1999 IEEE Int. Workshop on Memory Tech., Design and Testing, San Jose, CA, USA, p.102-109.). The chip has an adjustable cell capacity that can be selected from among 1, 1.5, 2 and 2.5 bits per cell. Fractional bits arise when groups of two or more cells are considered together. Thus if each cell in a pair stores one of six possible levels, then each cell has a capacity of 2.5 bits. The test chip should facilitate the experimental characterization of the proposed MLDRAM scheme.
具有可调单元容量的多级DRAM的设计
多层DRAM (MLDRAM)通过使用两个以上的小区信号电平,比传统DRAM增加了每个小区的存储容量。设计MLDRAM的关键挑战是,尽管存在芯片上噪声和集成电路(IC)生产中不可避免的电路参数微小变化,但要确保使用更紧密间隔的信号电平可靠运行。本文描述了一种测试芯片,该芯片实现了Birk等人提出的固有平衡和鲁棒的MLDRAM方案。存储器技术研讨会,设计与测试,圣何塞,加州,美国,p.102-109。该芯片具有可调节的单元容量,可以从每个单元1,1.5,2和2.5比特中进行选择。当两个或两个以上的细胞组合在一起考虑时,会出现分数位。因此,如果一对中的每个单元存储六个可能级别中的一个,则每个单元的容量为2.5位。测试芯片应便于所提出的MLDRAM方案的实验表征。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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