Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution [CMOS]

Abstract

The internal damage issue caused by ESD stress was investigated through a real case of high-voltage driver IC with separated power pins. After the HBM ESD tests applied on silicon chips of the original design, failure analysis was done with the help of OM and SEM to find out the failure spots. The results of failure analysis show that the internal damages on the interface circuit of two circuit blocks are caused due to the absence of the VDD-to-VSS power-rail ESD cell and the ESD cell of connecting different ground lines. By using the proposed effective ESD protection solution, the HBM ESD robustness of the high-voltage driver IC product can be improved to greater than 2.0kV.