Analysis and Design of a High-Efficiency Class-EM Power Amplifier

Abstract

The Class-EM power amplifier (PA) offers the possibility of achieving high-efficiency operations at high operating frequencies while using slow-switching transistors. This is made possible by the adoption of the ZVS/ZVDS/ZCS and ZCDS conditions on the main circuit and the adoption of the ZVS condition on the auxiliary circuit. In this paper, we present the analysis and design of a new topology of the Class-EM PA incorporating a finite DC-feed inductance and an isolation circuit, rendering it more attractive for implementations. Furthermore, we propose a novel transmission-line load network that provides the drain of the transistor with the required load impedances at the fundamental frequency as well as at even and odd harmonic frequencies for the main and the auxiliary circuits. The concept is verified through harmonic-balance simulations with the PA exhibiting a peak drain efficiency of 90.3%, a peak power added efficiency of 86.7%, and a peak output power of 41.2 dBm at an operating frequency of 1.5 GHz.