SPICE and IBIS modeling kits the basis for signal integrity analyses

Abstract

Reliable high speed board design requires a thorough analog analyzation of interconnect traces. Consequently a broad spectrum of signal integrity simulation tools has been developed and is readily available on the market to satisfy customers needs. All software tools require a large amount of data that describe electrical behavior of the integrated components involved at the interconnect traces. In this paper for the first time two sets of data for signal integrity analyses, SPICE and IBIS modeling kits, are outlined, discussed and compared to each other. The information of the kits provides the user with all data to perform buffer modeling, therefore enabling signal integrity analysis and synthesis on printed circuit boards.