Task Partitioning-An Efficient Scalable Pipelined Digital Design Scheme

Abstract

Digital circuits are designed after careful investigation of implementation constraints and limitations. Implemented circuits, whether realized on FPGA or an ASIC is developed, it is made sure that resulting design should be optimized with respect to processing speed and area occupied. Much informative work has been already proposed and effective results have obtained in the research field of processing speed and area optimization. In this paper, the concept of hierarchical concurrent flow graph (HCFG) is utilized to present proposed coarse grained layered scalable concurrent image compression (LSCIC) precoder design with pipelined scheme. This design causes all modules to operate concurrently for fast and minimum data loss operation. This scheme will not only highlight the task partitioning procedure to operate all modules in parallel but also gives rise to the concept of pipelining with reasonable number of stages so that system remains optimized. Moreover, practical solutions acquired by simulating tools are presented in this paper with appropriate substantiation. This paper also addresses the issue of selected FPGA resource utilization depending upon the complexity of operation and hardware components placed in corresponding module.