ATPG for Incomplete Testing of SOC Considering Bridging Faults

Abstract

Nowadays System on Chip (SOC) is used widely. Clients require gadgets that can handle several applications progressively. Due to an increase in the number of applications, the number of cores embedded in SOC increased too. Each core has a large number of components which increases the probability of occurring of bridging faults in SOC. Efficient testing of these faults is necessary. Testing larger SOC needs large test data volume (TDV), large test access time (TAT). It is hard to store this large amount of test data. It requires a large amount of time to process this test data which makes the testing sluggish. Testing is more complicated for large SOCs. Various traditional methods for testing bridging faults are already proposed to test SOC thoroughly. These strategies are accurate but more expensive in terms of testing resources and the cost of testing. A large number of cores in SOC leads to long TAT which is infeasible sometimes. In this paper, a method is proposed to test the bridging faults and to reduce the TDV and TAT. We propose an efficient method for incomplete testing of SOC considering bridging faults which affectively reduces the TDV but with a little compromise with the fault coverage. In this method, essential bridging faults are considered and a heuristic optimization technique is utilized to improve the TDV while compromising with the quality of testing.